? semiconductor components industries, llc, 2015 march, 2015 ? rev. 10 1 publication order number: mc14029b/d mc14029b binary/decade up/down counter the mc14029b binary/decade up/down counter is constructed with mos p?channel and n?channel enhancement mode devices in a single monolithic structure. the counter consists of type d flip?flop stages with a gating structure to provide toggle flip?flop capability. the counter can be used in either binary or bcd operation. this complementary mos counter finds primary use in up/down and difference counting and frequency synthesizer applications where low power dissipation and/or high noise immunity is desired. it is also useful in a/d and d/a conversion and for magnitude and sign generation. features ? diode protection on all inputs ? supply voltage range = 3.0 vdc to 18 vdc ? internally synchronous for high speed ? logic edge?clocked design ? count occurs on positive going edge of clock ? asynchronous preset enable operation ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? pin for pin replacement for cd4029b ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? this device is pb?free and is rohs compliant maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8?second soldering) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. temperature derating: ?d/dw? packages: ?7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. www. onsemi.com marking diagram soic?16 d suffix case 751b 14029bg awlyww a = assembly location wl = wafer lot yy, y = year ww = work week g = pb?free indicator see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 1 16
mc14029b www. onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 p1 p2 q2 clk v dd b/d u/d q1 p0 p3 q3 pe v ss c out q0 c in truth table carry in up/down preset enable action 1 x 0 no count 0 1 0 count up 0 0 0 count down x x 1 preset x = don?t care ordering information device package shipping ? mc14029bdr2g soic?16 (pb?free) 2500 units / tape & reel NLV14029BDR2G* soic?16 (pb?free) 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc14029b www. onsemi.com 3 electrical characteristics (voltages referenced to v ss ) characteristic symbo l v dd vdc ?55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? leve l v in = v dd or 0 ?1? leve l v in = 0 or v dd v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? leve l (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ?1? leve l (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) (v ol = 0.4 vdc) sin k (v ol = 0.5 vdc) (v ol = 1.5 vdc) i oh 5.0 5.0 10 15 ?3.0 ?0.64 ?1.6 ?4.2 ? ? ? ? ?2.4 ?0.51 ?1.3 ?3.4 ?4.2 ?0.88 ?2.25 ?8.8 ? ? ? ? ?1.7 ?0.36 ?0.9 ?2.4 ? ? ? ? madc i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance, (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc total supply current (notes 3 & 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.58 a/khz) f + i dd i t = (1.20 a/khz) f + i dd i t = (1.70 a/khz) f + i dd adc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.001.
mc14029b www. onsemi.com 4 switching characteristics (note 5) (c l = 50 pf, t a = 25 c) characteristic symbol v dd all types unit min typ (note 6) max output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time clk to q t plh , t phl = (1.7 ns/pf) c l + 230 ns t plh , t phl = (0.66 ns/pf) c l + 97 ns t plh , t phl = (0.5 ns/pf) c l + 75 ns clk to c out t plh , t phl = (1.7 ns/pf) c l + 230 ns t plh , t phl = (0.66 ns/pf) c l + 97 ns t plh , t phl = (0.5 ns/pf) c l + 75 ns c in to c out t plh , t phl = (1.7 ns/pf) c l + 95 ns t plh , t phl = (0.66 ns/pf) c l + 47 ns t plh , t phl = (0.5 ns/pf) c l + 35 ns pe to q t plh , t phl = (1.7 ns/pf) c l + 230 ns t plh , t phl = (0.66 ns/pf) c l + 97 ns t plh , t phl = (0.5 ns/pf) c l + 75 ns pe to c out t plh , t phl = (1. 7 ns/pf) c l + 465 ns t plh , t phl = (0.66 ns/pf) c l + 192 ns t plh , t phl = (0.5 ns/pf) c l + 125 ns t plh , t phl 5.0 10 15 ? ? ? 200 100 90 400 200 180 ns t plh , t phl 5.0 10 15 ? ? ? 250 130 85 500 260 190 ns t plh , t phl 5.0 10 15 ? ? ? 175 50 50 360 120 100 ns t plh , t phl 5.0 10 15 ? ? ? 235 100 80 470 200 160 ns t plh , t phl 5.0 10 15 ? ? ? 320 145 105 640 290 210 ns clock pulse width t w(cl) 5.0 10 15 180 80 60 90 40 30 ? ? ? ns clock pulse frequency f cl 5.0 10 15 ? ? ? 4.0 8.0 10 2.0 4.0 5.0 mhz preset removal time the preset signal must be low prior to a positive?going transition of the clock. t rem 5.0 10 15 160 80 60 80 40 30 ? ? ? ns clock rise and fall time t r(cl) t f(cl) 5.0 10 1 5 ? ? ? ? ? ? 15 5 4 s carry in setup time t su 5.0 10 15 150 60 40 75 30 20 ? ? ? ns up/down setup time 5.0 10 15 340 140 100 170 70 50 ? ? ? ns binary/decade setup time 5.0 10 15 320 140 100 160 70 50 ? ? ? ns preset enable pulse width t w 5.0 10 15 130 70 50 65 35 25 ? ? ? ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14029b www. onsemi.com 5 figure 1. power dissipation test circuit and waveform v dd i d 500 pf 0.01 f ceramic pulse generator pe c in b/d u/d clk p0 p1 p2 p3 c out q3 q2 q1 q0 c l c l c l c l c l v dd v ss 20 ns 20 ns clk 50% 90% 10% variable width figure 2. switching time test circuit and waveforms programmable pulse generator v dd pe c in b/d u/d clk p0 p1 p2 p3 c out q3 q2 q1 q0 c l v ss c l c l c l c l t w t su t rem 1/f cl 50% 50% t w c out only t tlh t plh t plh t phl t thl 90% 10% 90% 10% 20 ns carry in or up/down or binary/decade clock preset enable q0 or carry out v dd v ss v dd v ss v dd v ss v oh v ol
mc14029b www. onsemi.com 6 timing diagram clock carry in up/down binary/decade pe p0 p1 p2 p3 q0 q1 q2 q3 carry out count 012345678987654321009670 figure 3. divide by n bcd down counter and timing diagram (shown for n = 123) q3 q2 q1 q0 p3 p2 p1 p0 clk c out u/d b/d q3 q2 q1 q0 p3 p2 p1 p0 clk c out u/d b/d q3 q2 q1 q0 p3 p2 p1 p0 clk c out u/d b/d c in pe c in pe c in pe mc14029b msd mc14029b mc14029b lsd output input clock 1" 2" 3" v dd v dd v dd v dd clock c out 1 (lsd) c out 2 c out 3 (msd) pe count 123 122 121 120 119 101 100 99 11 10 9 1 0 123 122 *t w 900 ns @ v dd = 5 v
mc14029b www. onsemi.com 7 logic diagram binary/decade preset enable carry in up/down clock 9 1 5 10 15 4p0 12p1 13p2 3 p3 2q3 14 q2 11 q1 6q0 7 carry out pe te clk p3 q3 q3 pe te clk p2 q2 q2 pe te clk p1 q1 q1 pe te clk p0 q0 q0
mc14029b www. onsemi.com 8 package dimensions soic?16 d suffix plastic soic package case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc14029b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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